A Low-Power 0.13pm CMOS OC-48 SONET and XAUI Compliant SERDES

The design of a continuous rate octal 1.0 to 3.2 Gb/s serializer/deserializer circuit that meets SONET and XAUI requirements is presented. The performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications. This is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0 . 1 3 p digital CMOS technology, the part exhibits less than 5mUI r.m.s. jitter and the 1.2 mm2 transceiver dissipates 160mW. Introduction The building of networks to handle voice, data and Internet Protocol traffic has created a great need for multi-gigabit rate transceivers. This paper describes the design of an octal Serializer / Deserialize1 (SERDES) macro that covers a data rate ranging from 1.0 to 3.2 Gb/s. At 2.488 Gb/s the device exceeds OC-48 SONET jitter generation and jitter tolerance specifications. Novel design techniques are used in the chip, particularly in the phase lock loops (PLLs) of the transmitter and receiver circuits, to achieve low jitter generation in a harsh ASIC environment while dissipating low power. The device is implemented in a standard 0.1.3pn digital CMOS process and has been laid out for integration with flip-chip compatible ASICs. The block diagram of the SERDES is shown in Figure 1 . A single master-slave transmit PLL drives all eight transmitters to minimize power dissipation and to facilitate synchronization of the transmitters. In the receive direction, each channel has an independent analog PLL based clock and data recovery (CDR) block followed by a demultiplexer. Use of analog CDRs eliminates the need to route multi-phase high-speed clocks across eight receiver channels as would be required by digital or analog phase rotator approaches [1,2]. The eight receive CDRs share a common receive master PLL to achieve lowjitter generation as will be described later. The octal SERDES contains programmable registers to configure and monitor the transceivers as well as activate modes for production testing and characterization. Since a high-speed low-jitter clock is central for any SERDES implementation, the architecture of a PLL to generate such a clock isdescribed first in section I. The serializer is described in section 11, and the deserializer in section 111. Layout considerations for flip-chip packaging are discussed in section IV followed by experimental results in section V and conclusions in section VI I. PLL Architecture One of the biggest challenges in the PLL design is to achieve low jitter while maintaining a wide lock range from 1.0 to 3.2 Gb/s over all process conditions and temperatures. In any CMOS process this requirement is challenging, but in 0 . 1 3 ~ technology the challenge is even greater because the voltage tuning range that can be applied to the voltage-controlled oscillator (VCO) is less than 1 V. A wide lock range requires the VCO to have a large gain, however, low jitter generation necessitates a small VCO gain. These conflicting requirements can be solved in many different ways. One approach is to use a digitally programmable VCO as discussed in [3] to perform a coarse tuning at power up to remove process variations that affect the center frequency of the VCO. However, the gain of the VCO must still remain relatively high to accommodate temperature variations. In this design, a continuous master-slave calibration scheme is used. The linearized model of the master-slave PLL technique is depicted in Figure 2. The master PLL shown on top is designed to have a very high gain VCO so that it can lock over the entire 1.0 3.2 GHz frequency range for all process, temperature and power supply conditions. The tuning signal of the master VCO serves as the pedestal or continuous coarse tuning control for the slave VCO, which is similar to the master VCO but with a lower gain. The numerical subscripts 1 and 2 in Figure 2 and the equations below refer to the master and slave, respectively. The pedestal signal from the master places the slave VCO at nearly the correct operating frequency. Thus, the slave PLL only needs to fine tune the VCO via a low gain path. The gain of the slave VCO can then be made much smaller than that of the master VCO. The effect of any noise from the master affecting the slave can be analyzed with the help of Figure 2. Perhaps the single largest source of noise in a ring oscillator based PLL is the phase noise of the VCO indicated as 0,. The pedestal output signal from the master PLL will have a noise component V,, primarily from the inherent phase noise e., of the master VCO. The resulting transfer function is